# Verification Engineer  - Verification, Verilog, UVM

**Job Details:**
- **Location:** San Jose, CA
- **Type:** Permanent
- **Salary:** $140,000 - $190,000 Annually
- **Posted 3 weeks ago**
- **Job ID:** 937143

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## Job Description

Verification Engineer Position Overview We are seeking a Verification Engineer to develop and execute verification strategies for complex digital designs and SoC blocks. The role focuses on building robust SystemVerilog/UVM testbenches, creating directed and constrained-random tests, automating verification flows with scripting, and collaborating with RTL designers and integration teams to ensure

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